This invention is in the field of electronic circuits, and is more specifically directed to switched-capacitor circuits such as useful in data converter circuits.
Despite the continuing trend toward the digitization of electronic circuits and systems over recent years, modern electronic systems must still often process and generate electrical signals in the analog domain. For example, analog signals are transmitted and received in many modern communications technologies, and analog signals are used in instrumentation and control systems. Data converter circuits are therefore required to provide an interface between the digital and analog domains, especially in those systems in which digital signal processing is applied. As is fundamental in the art, analog-to-digital converters (ADCs) convert analog measurements or signals into the digital data to which digital signal processing is applied. Conversely, digital-to-analog converters (DACs) convert digital data into analog signals for transmission or actuation of a physical device.
Advances in modern data converter circuits have resulted in extremely precise, high-speed, data conversion functions. For example, ADCs with resolutions of from sixteen to twenty-two bits, at sample rates in the thousands of samples per second, are now available from Texas Instruments Incorporated. This level of performance requires not only very rapid switching speeds, but also an extremely high degree of precision. Accordingly, difficult tradeoffs are involved in the design of modern data converter circuits.
A well-known type of analog-to-digital converter is the so-called pipelined ADC, as will now be described relative to FIG. 1. In this example, the pipelined ADC has three stages 100 through 102, each of which will generate one or more digital bits corresponding to the amplitude of an analog input signal. First, or most significant, pipeline stage 100 receives the input analog signal at terminal ANALOG_IN, generates one or more digital bits on output D0, and also generates an analog residue that is presented to the next pipeline stage 101. Pipeline stage 101 similarly generates one or more digital bits on output D1 from this residue from stage 101, and generates an analog residue that is forwarded to the next pipeline stage 102. Stage 102 generates one or more digital bits on output D2 corresponding to the residue from stage 101, and forwards a residue to a next stage (not shown) if present. Digital outputs D0 through D2 are connected to digital correction function 11, which combine the digital bits from ADCs 3 into the eventual digital output on lines DIGITAL_OUT.
Pipeline stages 100 through 102 are similarly constructed as one another. In this conventional construction, with reference to stage 100 by way of example, the input to the stage is connected to the input of sample-and-hold circuit 2, which is clocked to receive and store an analog voltage corresponding to the voltage at that input. The output of sample-and-hold 2 is applied to the input of analog-to-digital converter (ADC) 3, and also to an input of analog adder 4. ADC 3 generates a digital output consisting of one or more bits on output line D0; this digital output is also applied to the input of digital-to-analog converter (DAC) 5. In many popular cases, the pipelined ADC generates “1.5” bits per stage 10, referring to each ADC 3 generating a two bit output, but with some of the bits digitally combined by digital correction function 11 to effect digital error correction, as known in the art. DAC 5 also receives this digital value, and generates an analog signal corresponding to a comparison of this digital value against one or more reference voltages (generated by bandgap reference circuit 6 in this example). This analog signal is subtracted from the analog input signal, by adder 4, to generate a residue signal to be forwarded to, and digitized by, the next stage 101. This residue amounts to the difference between the input analog signal itself and an analog signal corresponding to the digital “integer” approximating the amplitude of the input analog signal; the next stage 101 thus digitizes this residue value to produce the next-most significant digital bit or bits. Gain stage 7 “gains up” the residue from adder 4, so that the residue analog signal will vary over the full input dynamic range of next stage 101, to avoid loss of sensitivity from stage to stage.
As is well known in the art, the digital data presented at digital output outputs D0 through D2 are combined by digital correction function 11 into a digital output word that approximates the amplitude of the analog input signal. This combining can account for some error in the digitization of each stage 100 through 102, and as such the necessary precision of ADCs 3 in each of stages 100 through 102 can be relatively loose. However, DACs 5 must be quite precise, as the output of DACs 5 derive the residue signal that is passed along to the next stage, and is amplified by gain stage 7. Any error produced by a given DAC 5 thus directly appears in the output digital signal. Accordingly, the precision of DACs 5 is a limiting factor in the accuracy and performance of the pipelined ADC.
FIG. 2 illustrates an example of a conventional switched-capacitor circuit 8, which effects the functions of DAC 5, adder, 4, and gain stage 7 in one of stages 10 in the conventional pipelined ADC of FIG. 1. Of course, many variations in the construction of circuit 8 are known. This type of switched-capacitor circuit is commonly referred to in the art as a “multiplying DAC”, or “MDAC”, in that the circuit generates an analog residue signal corresponding to an input analog level relative to a digital input, and that is multiplied by a gain value. In this example, assuming that each pipeline stage 10 produces 1 bit or 1.5 bits per stage (the case of 1.5 bits per stage referring to the number of output bits at DIGITAL_OUT being 1.5 times the number of stages 10), the output voltage Vout is intended to be twice the difference between input voltage Vin from sample-and-hold circuit 2, and a selected reference voltage VREFP or VREFN, where the reference voltages VREFP and VREFN define the full scale voltage between adjacent digital levels, and correspond to the output voltage swing of op amp 9. The reference voltage VREFP is selected if the input voltage Vin was digitized to a “1” bit, while the reference voltage VREFN is selected if the input voltage Vin was digitized to a “0” bit. Switched-capacitor circuit 8 of FIG. 2 includes one pair of capacitors CA, CB, which corresponds to the case in which one bit (or 1.5 bits, in which case only the MSB is forwarded to DAC 5) of digital resolution is provided by ADC 3. As known in the art, if ADC 3 provides a multiple bit output (up to as many as five bits, in some modern pipelined ADCs), additional capacitor pairs that are configured and operate in the same fashion as capacitors CA, CB will be provided in circuit 8, with the number of capacitor pairs that are switched into the circuit corresponding to the digital output of ADC 3.
As evident from FIG. 1, input voltage Vin is the voltage output from sample-and-hold 2 within the same stage 10 in which DAC 5 resides. Referring back to FIG. 2, pass switches S1, S2 are each connected between this input voltage Vin and a first plate of respective capacitors CA, CB. Capacitors CA, CB have the same capacitance, in this example. The other plates of capacitors CA, CB are connected together, and to an inverting input of operational amplifier (“op amp”) 9; these capacitor plates are also connected to ground via pass switch S6. The first plate of capacitor CA is connected via MDAC switch block 11 to receive one of the reference voltages VREFP or VREFN or to ground, via a corresponding one of switches SP, SN, SG, respectively, in response to the digital value from ADC 3. The first plate of the capacitor CB is connected to the output of op amp 9 via pass switch S4. Pass switches S1, S2, and S6 are clocked to be closed during clock phase Φ1, while pass switch S4 and the appropriate switch SP, SN, SG in MDAC switch block 11 are closed during clock phase Φ2. Clock phases Φ1, Φ2 are non-overlapping clock phases; indeed, clock phase Φ2 may be simply clock phase Φ1, logically inverted.
In operation during “sample” clock phase Φ1, pass switches S1, S2, and S6 are closed, pass switch S4 is open, and all of MDAC switches SP, SN, SG are also open. Pass switches S1, S2 connect the input voltage Vin to capacitors CA, CB; the opposite plates of capacitors CA, CB are connected to ground by the closed state of switch S6. Capacitors CA, CB thus both charge to input voltage Vin during this clock phase. In “amplify” clock phase Φ2, pass switches S1, S2, and S6 are open, and pass switch S4, and the selected one of reference voltage switches SP, SN, SG, are closed. During this clock phase, the capacitor CB becomes the feedback capacitor, and capacitor CA receives the selected reference voltage VREFP or VREFN, as the case may be. To the extent that the selected reference voltage differs from input voltage Vin, charge sharing between capacitors CA and CB occurs. One can analyze the circuit by equating the sum of the charge on capacitors CA and CB during clock phase Φ1 with the sum of the charge on these capacitors during the next clock phase Φ2. In other words:−VinCA−VinCB=−VoutCB−VREFP/REFNCA  (1)where reference voltage VREFP/REFN is the selected reference voltage VREFP or VREFN, and where the positive polarity sign of the charge on capacitors CA, CB points toward the inverting input of op amp 9, at virtual ground. Solving for output voltage Vout, and assuming identical capacitance C for capacitors CA and CB, the operation of switched capacitor circuit 8 amounts to:                               V          out                =                  2          ⁢                      (                                          V                in                            -                                                V                  REF                                2                                      )                                              (        2        )            In this manner, the circuit of FIG. 2 generates an output voltage Vout that corresponds to a the difference between input voltage Vin and reference voltage VREF at the midpoint between reference voltages VREFP and VREFN.
Another known construction of an MDAC, in this case using differential inputs, is illustrated in FIG. 3 with reference to switched-capacitor circuit 8′, which includes differential op amp 9′ having positive and negative polarity inputs and outputs. Switched-capacitor circuit 8′ in this conventional arrangement receives inputs Vin+, Vin− that correspond, by their difference, to the sampled input signal from sample-and-hold 2 (FIG. 1). Switched-capacitor circuit 8′ again receives reference voltages VREFP, VREFN that correspond to the maximum output swing of op amp 9′, and that are applied to circuit 8′ via MDAC switch block 37, controlled by the output of ADC 3. In this differential case, MDAC switch block 37 includes switches S31P and S35N for applying a positive differential reference voltage (VREFP−VREFN) across the sampling plates of capacitors C2, C3, includes switches S31N and S35P to apply a negative differential reference voltage (VREFN−VREFP) across the sampling plates of capacitors C2, C3, and also includes switch S33 that shorts capacitors C2 and C3 together (a zero differential reference voltage). The differential reference voltage applied to capacitors C2, C3 is determined by the result from the associated ADC stage, as before. Typical values of reference voltages VREFP, VREFN in a modern conventional pipelined ADC are 2.0 volts and 1.0 volts, respectively, corresponding to the maximum and minimum voltages at the positive and negative polarity outputs of op amp 9′ being 2.0 volts and 1.0 volts, respectively. This correspondence between reference voltages VREFP, VREFN and the output voltages of op amp 9′ is selected in order to use same-sized capacitors C1, C2, C3, C4 in the sample and feedback loops of switched-capacitor circuit 8′. Again, the differential output Vout of op amp 9′ effectively corresponds to the difference between input voltages Vin+, Vin− and midpoint reference voltage VREF between reference voltages VREFP, VREFN defined by:                                           V            REF                    2                =                                            V              REFP                        -                          V              REFN                                2                                    (        3        )            
Switch S10, which is controlled by clock phase Φ1, connects input voltage Vin+, to capacitor C1, the other side of which is connected to the negative polarity input of op amp 9′. Switch S11, also controlled by clock phase Φ1, connects input voltage Vin+, to capacitor C2, the other side of which is connected to the negative polarity input of op amp 9′. As mentioned above, one of switches S31P, S31N, and S33 in MDAC switch block 37 is closed during non-overlapping clock phase Φ2 to connect capacitor C2 to reference voltage VREFP or VREFN, or to capacitor C3, depending on the result from ADC 3. Capacitor C1 is connected as a feedback capacitor to the positive polarity output of op amp 9′ by switch S13, which is clocked by clock phase Φ2. Switch S33 within MDAC switch block 37 is provided to discharge, or at least equalize, the charge at capacitors C2, C3 prior to the next sample.
Similarly, switch S20 of DAC 5′ is controlled by clock phase Φ1, and connects input voltage Vin− to capacitor C3, the other side of which is connected to the positive polarity input of op amp 9′. Switch S21 is also controlled by clock phase Φ1, and connects input voltage Vin−, to capacitor C4, the other side of which is also connected to the positive polarity input of op amp 9′. And one of switches S35P, S35N, and S33 in MDAC switch block 37 is closed during non-overlapping clock phase Φ2 to connect capacitor C3 to reference voltage VREFP or VREFN, or to capacitor C2, depending on the result from ADC 3. Capacitor C4 is connected as a feedback capacitor to the negative polarity output of op amp 9′ by switch S23, which is clocked by clock phase Φ2.
In addition, switch S15 connects the positive and negative inputs of op amp 9′ together in response to clock phase Φ1. And in this conventional construction, capacitors C1, C2, C3, C4 all have the same capacitance as one another.
Again, in this example, switched-capacitor circuit 8′ is constructed in a manner corresponding to the pipelined ADC generating one bit, or 1.5 bits, per stage 10. If each stage 10 generates multiple digital bits, then additional pairs of capacitors for each input to op amp 9′ will be provided, along with switches that include (or isolate) those additional capacitors depending on the digital output from ADC 3. In any case, however, the reference voltages VREFP, VREFN in this conventional pipelined ADC remain at the op amp output levels, regardless of the number of bits per stage.
In operation, clock phase Φ1 is the sample clock phase, during which time the input voltages Vin+, Vin− are applied to capacitors C1, C2, C3, C4 via switches S10, S11, S21, S20, respectively, while switch S15 also shorts the positive and negative polarity inputs of op amp 9′ together. Switches S12, S13, S22, S23 are all open during this sample phase. In this sample phase, therefore, the input voltages Vin+, Vin− are established across capacitors C1, C2, C3, C4.
During amplify clock phase Φ2, the selected differential reference voltage are applied to capacitors C2, C3, while capacitors C1, C4 are connected into the feedback loop of op amp 9′. Charge sharing among capacitors C1, C2, C3, C4 during this clock phase thus develops a voltage at the negative polarity input to op amp 9′ that corresponds to the difference between input voltage Vin+ and the selected differential reference voltage±|VREFP−VREFN| or zero volts, while a voltage is developed at the positive polarity input that corresponds to the difference between input voltage Vin− and the selected differential reference voltage. The difference between these two voltages at the input to op amp 9′ thus drives a differential output voltage Vout that, through charge sharing as discussed above relative to FIG. 2, corresponds to the differential input voltage between voltages Vin+, Vin− and the midpoint reference voltage VREF/2 as defined by equation (3) above.
As mentioned above, the precision with which DAC 5, 5′ operates in the pipelined ADC operation is critical in the precision of the eventual result. It has been observed, in connection with this invention, that errors in the reference voltages VREFP, VREFN, as the case may be, directly injects error in the residue that is passed from one stage 10 to the next in the pipelined ADC. Specifically, as known in the art, each digital output bit from a given stage 10 of the pipelined ADC can be defined as:                     int        ⁢                                                      V              in                                      (                                                V                  REF                                2                            )                                                ×                  2          n                                    (        4        )            where Vin is the input residual voltage to the stage 10 (gained up to full scale by gain stage 7 in the preceding stage 10), and where n is the bit position generated by the given stage 10. As evident from this equation (4), error in the reference voltages VREFP, VREFN translates directly into error in the digital output from the pipelined ADC.
It has also been observed, according to this invention, that there are many sources of significant error in the reference voltages applied to pipelined ADCs. The most significant cause of such error is noise that couples to the reference voltages from the rapid switching of transistors in the circuit. As described in U.S. Pat. No. 6,249,240 B1, commonly assigned with this application and incorporated herein by this reference, another source of instability in the reference voltages applied to MDACs in pipelined ADCs is the load of the MDACs themselves, which can be data-dependent as this load varies with the input voltages input voltages Vin+, Vin−. While one could wait for this induced noise to settle, prior to operation of a stage 10, this approach is of course inconsistent with the desire for extremely high sample rate operation in modern pipelined ADCs.